Designing circuits, such as those implemented on field programmable gate arrays (FPGAs), can be a complex process. Meeting timing requirement(s) is one of the most challenging problems that circuit designers face, and can be even more challenging in an FPGA implementation when having to connect application-specific logic to hardwired components having fixed pin locations. Automated computer-aided design (CAD) implementation tools help circuit designers; however, automated place-and-route electronic design automation (EDA) solutions may be unable to resolve timing issues in the circuit design. As a result, circuit designers have to spend a lot of manual effort and time trying to close timing.